Project Name::DES Cryption on FPGAs Board by VHDL language
์Description:: DES Algorithm
Main Algorithm
There are two permutations of the data, one at the beginning of the algorithm, and another, the inverse of the first permutation at the end of the algorithm. The body of the algorithm divides the data into two 32-bit halves. Each round there is a new left half and a new right half produced using the previous halves and a 48-bit subkey, which is calculated by a key scheduling algorithm.
The Encryption Scheme
In the Data Encryption Scheme there are 16 such rounds using 16 different subkeys. In each round a function, F, described below, is created using the right half and subkey. The left half is then XOR'ed with the output of the function F. Between each round the left half and right halves are switched.
The F Function
The F function expands the 32-bit right half to 48 bits by duplicating 16 bits. The result is XOR'ed with the 48-bit subkey. This is then passed through eight S boxes, each one of which maps six bits into four using a particular look-up table. The output of the S boxes is concatenated and permuted once to give the final output of the F function.
link about DES